There are currently two approaches to register files used in microcontrollers and microprocessors. One of the approaches allows aligned accesses to bytes, words and double words (Dwords) for the entire register file. This approach requires more bits to encode register addresses, resulting in longer instructions and larger code. For example a register file of 64 bytes requires 6 bits to encode each of the 64 8-bit register references. Therefore, an instruction with two register references take 12 bits to encode the two register addresses. With an instruction length of two bytes, only four bits remain for opcode encoding which cuts down the number of possible instructions substantially. Using an instruction length of three bytes increases the code size and requires higher bus bandwidth.
The other approach is taken by many RISC architectures. These architectures have multiple (typically 32) 32-bit registers (128 bytes in total), each of which can also be used as 16 and 8-bit registers. This approach reduces the utilization of the register file. If, for example, a register is used as an 8-bit register, the remaining three bytes of the 32-bit register cannot be utilized. This results in requiring more registers for efficient compiler implementation, which in turn results in longer instructions to encode register addresses (commonly 32-bit) and lower code density. This approach is suited for architectures where performance is of highest importance and cost is of secondary importance.